1. Field of the Invention
The present invention relates generally to a communication system, and, in particular, to an apparatus and method for receiving signals in a communication system.
2. Description of the Related Art
Generally, communication systems have developed to provide terminals capable of providing high-speed, high-capacity data transmission/reception services. Therefore, the communication systems consider using Low Density Parity Check (LDPC) codes, which are channel codes suitable for high-speed, high-capacity data transmission/reception.
With reference to the block diagram of FIG. 1, a description is provided of a signal transmission apparatus in a general communication system using LDPC codes. Referring to FIG. 1, the signal transmission apparatus includes an encoder 111, a modulator 113 and a transmitter 115. If desired transmission information data, i.e. information vector s, is generated in the signal transmission apparatus, the information vector s is delivered to the encoder 111. The encoder 111 generates a codeword vector c, i.e. LDPC codeword, by encoding the information vector s using a predetermined coding scheme and outputs the codeword vector c to the modulator 113. Herein, the coding scheme is an LDPC coding scheme. The modulator 113 generates a modulation vector m by modulating the codeword vector c using a predetermined modulation scheme and outputs the modulation vector m to the transmitter 115. The transmitter 115 performs transmission signal processing on the modulation vector m output from the modulator 113 and transmits the processed signal to a signal reception apparatus via an antenna.
With reference to the block diagram of FIG. 2, a description will now be made of a structure of a signal reception apparatus in a general communication system using LDPC codes.
Referring to FIG. 2, the signal reception apparatus includes a receiver 211, a demodulator 213 and a decoder 215. A signal transmitted by a signal transmission apparatus is received at the signal reception apparatus via an antenna, and the signal received via the antenna is delivered to the receiver 211. The receiver 211 performs reception signal processing on the received signal and outputs the processed reception vector r to the demodulator 213. The demodulator 213 demodulates the reception vector r output from the receiver 211 using a demodulation scheme corresponding to a modulation scheme used in a modulator, i.e. modulator 113, of the signal transmission apparatus and outputs the resulting demodulation vector x to the decoder 215. The decoder 215 decodes the demodulation vector x output from the demodulator 213 using a decoding scheme corresponding to a coding scheme used in an encoder, i.e. encoder 111, of the signal transmission apparatus, and outputs the decoded signal as a finally restored information vector ŝ. Herein, the decoding scheme, i.e. LDPC decoding scheme, uses an iterative decoding algorithm based on a sum-product algorithm, a detailed description of which is provided below.
The LDPC code is defined by a parity check matrix in which the major elements have a value of ‘0’ and the minor elements except for the elements having a value of ‘0’ have a non-zero value, for example, a value of ‘1’. The LDPC code can be expressed with a bipartite graph, and the bipartite graph is expressed with variable nodes, check nodes and edges connecting the variable nodes to the check nodes.
In addition, the LDPC code can be decoded in the bipartite graph using the iterative decoding algorithm based on the sum-product algorithm. The sum-product algorithm is a kind of a message passing algorithm, and the term ‘message passing algorithm’ refers to an algorithm of exchanging messages through the edges in the bipartite graph, and calculating and updating output messages from the messages input to the variable nodes or the check nodes.
With reference to the block diagram of FIG. 3, a description will now be made of a message passing operation in an arbitrary check node of a decoder using a general LDPC decoding scheme (hereinafter ‘LDPC decoder’).
FIG. 3 shows a check node #m 300 and a plurality of variable nodes 310, 320, 330 and 340 connected to the check node #m 300. In addition, Tn,m indicates a message passing from a variable node #n′ 310 to the check node #m 300, and En,m indicates a message passing from the check node #m 300 to a variable node #n 330. Herein, a set of all variable nodes connected to the check node #m 300 is defined as N(m) and a set determined by excluding the variable node #n 330 from N(m) is defined as N(m)\n. In this case, a message update rule based on the sum-product algorithm can be expressed as Equation (1):
                                                                    E                              n                ,                m                                                          =                      Φ            [                                          ∑                                                      n                    ′                                    ∈                                                            N                      ⁡                                              (                        m                        )                                                              ⁢                    \                    ⁢                                                                                  ⁢                    n                                                              ⁢                                                          ⁢                              Φ                (                                                                        T                                                                  n                        ′                                            ,                      m                                                                                        )                                      ]                          ⁢                                  ⁢                              Sign            ⁢                                                  ⁢                          (                              E                                  n                  ,                  m                                            )                                =                                    ∏                                                n                  ′                                ∈                                                      N                    ⁡                                          (                      m                      )                                                        ⁢                  \                  ⁢                                                                          ⁢                  n                                                      ⁢                                                  ⁢                          sign              (                              T                                                      n                    ′                                    ,                  m                                            )                                                          (        1        )            
In Equation (1), Sign(En,m) denotes a sign of a message En,m, |En,m| denotes a magnitude of the message En,m, and a function Φ(x) can be expressed as Equation (2):
                              Φ          ⁡                      (            x            )                          =                  -                      log            ⁡                          (                              tanh                ⁡                                  (                                      x                    2                                    )                                            )                                                          (        2        )            
With reference to the block diagram of FIG. 4, a description will now be made of an internal structure of a general LDPC decoder.
Referring to FIG. 4, the LDPC decoder includes a first memory 400, a check node processor 410 and a second memory 420. The first memory 400 stores the messages to be input to the check node processor 410, and the second memory 420 stores the messages output from the check node processor 410. The first memory 400 includes a plurality of, for example, dc sub-memories of a sub-memory #1 (M1) 400-1 to a sub-memory #dc (Mdc) 400-dc. The second memory 420 includes a plurality of, for example, dc sub-memories of a sub-memory #1 (M′1) 420-1 to a sub-memory #dc (M′dc) 420-dc. Although the memory for storing the messages to be input to the check node processor 410 and the memory for storing the messages output from the check node processor 410 are implemented with separate memories in FIG. 4, by way of example, the memory for storing the messages to be input to the check node processor 410 and the memory for storing the messages output from the check node processor 410 can be implemented with the same memory.
If an input dimension of the check node processor 410 is assumed to be dc, the dc input messages are stored in the sub-memory #1 (M1) 400-1 to the sub-memory #dc (Mdc) 400-dc, and the output messages mapped to the dc input messages are stored in the sub-memory #1 (M′1) 420-1 to the sub-memory #dc (M′dc) 420-dc. 
As described in FIGS. 3 and 4, in the message passing algorithm, the sum-product algorithm described in Equation (1) is an optimal scheme for decoding an LDPC code that can be expressed with a bipartite graph having no cycle. However, the use of the sum-product algorithm considerably increases complexity of implementation of check node processing (or check node operation), making the implementation difficult. Therefore, there is a need for an LDPC code decoding scheme for reducing complexity of check node processing.